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MWPC Configuration and Registers

Attached to this wiki page are the registers provided by Sten.

Specific implementations are documented on this page (please update with all information we know about!).

To login to the controller do:
$ telnet ftbfwc03 <port>

where the ports are:
  • 5000 - daq apps
  • 5001 - emergency access
  • 5002 - telnet sessions

be sure to log out of the sessions using "^]" (the ^ means ctrl)

Help info can be found in the telnet session by typing he (additional help pages are h1-h4)

Basic commands:

Read 16 registers in a row starting from <reg>
$ rdi <reg>

Read a single register
$ rd <reg>

Write a register
$ wr <reg> <value>

Preceding the above commands with "hc <tdc>" where tdc goes from 1-16 (using tdc 0 prints the info for all connected tdcs)

Write tdc threshold (input is hex, convert to volts: dec/4095*1.024, where dec is the hex value converted to decimal)
$ hc <tdc> wt 8 <hex>

Spill state register 0x0B

$ rd b
0002

The return value should cycle between 2 (out of the spill) and 8 (in the spill)
It may be cycling between 1 and 9. This is bad.

If not good, try

$ wr 1 c4
If TDCs are not in the correct state, try power cycling:
There are commands to power cycle the controller from telnet:
Reset the tdc ports:
$ pwrrst

Reset the controller:
$ reset

Those power cycles aren't off for long enough and the controller/tdcs may not come back in a happy state.
We have a network controllable power strip to do a hard power cycle.
To log into the strip you can:
  • create a tunnel to novabeamlinedaq00 (ssh -D 9999 -f -C -q -N ) then set up firefox for tunneling.
  • or log into the vnc session on novadaqbeamlin00 (ssh -L 5971:localhost:5951 -N -f -l novadaq novabeamlinedaq00.fnal.gov).

Then point firefox to ftbf-pdu08.fnal.gov (ask Mike or Andrew for the username and pw). You can now power cycle the channels connected to the strip

Display current controller and tdc spill headers: p0

Very useful to check if the controller is happy

From telnet

$ p0
Controllers Spill Data Header  (15000mS SpillGate)
 TotalWrdCnt  = 0000006A  (106 D)
 SpillCounter = 00000046  (70 D)
 RTC Year/Mon = 120A      (18/10)
 RTC Day/Hr   = F0F       (15/15)
 RTC Min/Sec  = 352E      (53/46)
 Trigger Cnt  = 00000000
 Status Bits  = 0
 Link Status  = 0
           TDC Spill Hdrs (1 <= 16)
 Input   Words       TDCnum   TrgCnt      Status
   1     00000006    0001     00000000    0008
   2     00000006    0002     00000000    0008
   3     00000006    0003     00000000    0008
   4     00000006    0004     00000000    0008
   5     00000006    0005     00000000    0008
   6     00000006    0006     00000000    0008
   7     00000006    0007     00000000    0008
   8     00000006    0008     00000000    0008
   9     00000006    0009     00000000    0008
  10     00000006    000A     00000000    0008
  11     00000006    000B     00000000    0008
  12     00000006    000C     00000000    0008
  13     00000006    000D     00000000    0008
  14     00000006    000E     00000000    0008
  15     00000006    000F     00000000    0008
  16     00000006    0010     00000000    0008

Things to check
  • The spill counter is incrementing
  • Trigger counts match between tdcs and controller
  • tdc status is 8 (anything else, usually 9, is bad)
  • tdc numbers are correct (if the controller is in a bad state they may be very crazy)

Internal Pulser

Setting are registers 7D, 7E, and 7F

$ rdi 70
   0    0    9    9    9    9    9    9    0    0    9    9    0    0    6    2 

The last 3 are the pulser settings

7D sets the rate (convert the value from hex to decimal then multiply by 0.0247 to get the Hz)
7E is the spill width (convert to decimal to get width in seconds)
7F is the inter-spill width (the dead time between spills)

Setting register 1 to EC turns on the pulser (E0 resets spill info and 0C turns on the pulser)
Setting register 1 to E4 turns off the pulser

See the register document for more info on register 1

rdi 20

$ rdi 20
  4c   4c   4c   4c   4c   4c   4c   4c   4c   4c   4c   4c   4c   4c   4c   4c

Should all be in sync. If not...

wr 1 4c

to, for example, write register 1 (second).