Front-end information » History » Version 30
Michael Wallbank, 07/01/2019 10:19 AM
1 | 1 | Michael Wallbank | h1. Front-end information |
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2 | 1 | Michael Wallbank | |
3 | 24 | Michael Wallbank | h2. V1742/V1495 channel mapping (Last Modified: July 1 2019) |
4 | 1 | Michael Wallbank | |
5 | 12 | Varun Raj | <pre> |
6 | 22 | Michael Wallbank | Input | Digitizer Channel |
7 | 22 | Michael Wallbank | ---------------------------------+------------------- |
8 | 22 | Michael Wallbank | Cherenkov | 0 |
9 | 22 | Michael Wallbank | ToF DS 5 (SiPM) | 4 |
10 | 22 | Michael Wallbank | ToF DS 6 (SiPM) | 5 |
11 | 22 | Michael Wallbank | ToF DS 7 (SiPM) | 6 |
12 | 22 | Michael Wallbank | ToF DS 8 (SiPM) | 7 |
13 | 22 | Michael Wallbank | ToF US 1 (PMT) | 8 |
14 | 22 | Michael Wallbank | ToF US 2 (PMT) | 9 |
15 | 22 | Michael Wallbank | ToF US 3 (PMT) | 10 |
16 | 22 | Michael Wallbank | ToF US 4 (PMT) | 11 |
17 | 22 | Michael Wallbank | ToF DS 1 (PMT) | 12 |
18 | 22 | Michael Wallbank | ToF DS 2 (PMT) | 13 |
19 | 22 | Michael Wallbank | ToF DS 3 (PMT) | 14 |
20 | 22 | Michael Wallbank | ToF DS 4 (PMT) | 15 |
21 | 1 | Michael Wallbank | </pre> |
22 | 1 | Michael Wallbank | |
23 | 12 | Varun Raj | <pre> |
24 | 25 | Michael Wallbank | Input | Trigger Channel | Description |
25 | 27 | Michael Wallbank | ---------------------------------+--------------------+---------------------------------------------------------------------------- |
26 | 26 | Michael Wallbank | WC 1 Logic | 0 | Wire chamber 1 (X|X & Y|Y) (40ns) -- First four trigger board inputs have additional M of 4 logic, M = {1,2,3,4} |
27 | 26 | Michael Wallbank | WC 2 Logic | 1 | Wire chamber 2 (X|X & Y|Y) (40ns) |
28 | 26 | Michael Wallbank | WC 3 Logic | 2 | Wire chamber 3 (X|X & Y|Y) (40ns) |
29 | 26 | Michael Wallbank | WC 4 Logic | 3 | Wire chamber 4 (X|X & Y|Y) (40ns) |
30 | 27 | Michael Wallbank | Scintillator Paddle 1 (Mock WC1) | 4 | Pad 1 at position of WC1 |
31 | 27 | Michael Wallbank | Scintillator Paddle 2 (Mock WC2) | 5 | Pad 2 at position of WC2 |
32 | 27 | Michael Wallbank | Scintillator Paddle 3 (Mock WC3) | 6 | Pad 3 at position of WC3 |
33 | 27 | Michael Wallbank | Scintillator Paddle 4 (Mock WC4) | 7 | Pad 4 at position of WC4 |
34 | 27 | Michael Wallbank | Readout Gate | 8 | $00 -> $00+T DAQ readout window (T ~ 40s) |
35 | 27 | Michael Wallbank | Switchyard Gate | 9 | $30 -> $36 gate; same readout gate as the MWPC Controller |
36 | 27 | Michael Wallbank | MWPC Off | 10 | Readout inhibit: TRUE when MWPC Controller is available to accept a new trigger (10us gate) |
37 | 27 | Michael Wallbank | Digitizer Busy | 11 | Readout inhibit: TRUE when the digitizer is done digitizing previous triggers (~O(100us)) |
38 | 27 | Michael Wallbank | WC Hardware Coincidence | 12 | Wire chamber trigger logic done in NIM bin; 30ns outputs for TDCs 2,3,4 (2 of 3 coincidence) in AND coincidence with 10ns output for TDC 1; see diagram below |
39 | 26 | Michael Wallbank | EMPTY | 13 | |
40 | 27 | Michael Wallbank | TOFPrompt Logic | 14 | Time-of-flight prompt trigger signal; 10ns DS ToF in coincidence in 65ns-delayed 10ns US ToF (fast particle ToF ~ 44ns); see diagram below |
41 | 27 | Michael Wallbank | TOFSlow Logic | 15 | Time-of-flight slow trigger signal; 10ns DS ToF in coincidence in 75ns-delayed 90ns US ToF (slow particle ToF > 44ns); see diagram below |
42 | 24 | Michael Wallbank | </pre> |
43 | 24 | Michael Wallbank | |
44 | 24 | Michael Wallbank | New proposed trigger board configuration: |
45 | 24 | Michael Wallbank | |
46 | 24 | Michael Wallbank | <pre> |
47 | 24 | Michael Wallbank | Input | Trigger Channel |
48 | 24 | Michael Wallbank | ---------------------------------+------------------- |
49 | 24 | Michael Wallbank | WC 1 Logic | 0 |
50 | 24 | Michael Wallbank | WC 2 Logic | 1 |
51 | 24 | Michael Wallbank | WC 3 Logic | 2 |
52 | 24 | Michael Wallbank | WC 4 Logic | 3 |
53 | 24 | Michael Wallbank | Scintillator Paddle 1 (Mock WC1) | 4 |
54 | 24 | Michael Wallbank | Scintillator Paddle 2 (Mock WC2) | 5 |
55 | 24 | Michael Wallbank | Scintillator Paddle 3 (Mock WC3) | 6 |
56 | 24 | Michael Wallbank | Scintillator Paddle 4 (Mock WC4) | 7 |
57 | 24 | Michael Wallbank | TOF US | 8 |
58 | 24 | Michael Wallbank | Switchyard Gate | 9 |
59 | 24 | Michael Wallbank | MWPC Off | 10 |
60 | 24 | Michael Wallbank | Digitizer Busy | 11 |
61 | 24 | Michael Wallbank | MWPC Coincidence | 12 |
62 | 24 | Michael Wallbank | TOF DS | 13 |
63 | 22 | Michael Wallbank | TOFPrompt Logic | 14 |
64 | 23 | Michael Wallbank | TOFSlow Logic | 15 |
65 | 12 | Varun Raj | </pre> |
66 | 10 | Michael Wallbank | |
67 | 8 | Michael Wallbank | h2. VME crate |
68 | 8 | Michael Wallbank | |
69 | 8 | Michael Wallbank | As user novadaq, the directory |
70 | 8 | Michael Wallbank | <pre> |
71 | 8 | Michael Wallbank | /home/nfs/novadaq/ |
72 | 8 | Michael Wallbank | </pre> |
73 | 8 | Michael Wallbank | on novabeamlinedaq00 contains some useful utilities to communicate with the hardware. All CAEN provided software. |
74 | 8 | Michael Wallbank | |
75 | 8 | Michael Wallbank | Run CAEN upgrader GUI: |
76 | 8 | Michael Wallbank | <pre> |
77 | 8 | Michael Wallbank | ./CAENUpgrader-1.6.3/CAENUpgraderGUI/CAENUpgraderGUI |
78 | 8 | Michael Wallbank | </pre> |
79 | 8 | Michael Wallbank | |
80 | 8 | Michael Wallbank | Run CAEN V1742 digitizer (outside of DAQ): |
81 | 8 | Michael Wallbank | <pre> |
82 | 8 | Michael Wallbank | wavedump-3.8.2/bin/wavedump /etc/wavedump/WaveDumpConfig_X742.txt |
83 | 8 | Michael Wallbank | </pre> |
84 | 8 | Michael Wallbank | |
85 | 8 | Michael Wallbank | Run CAEN VME module: |
86 | 8 | Michael Wallbank | <pre> |
87 | 8 | Michael Wallbank | ./CAENVMELib-2.50/sample/CAENVMEDemo V2718 <base address, in hex (beginning 0x)> <link> |
88 | 8 | Michael Wallbank | </pre> |
89 | 8 | Michael Wallbank | With this utilities, one can set the base address (option 2), set a register (option 1) and read etc. |
90 | 8 | Michael Wallbank | |
91 | 8 | Michael Wallbank | CAEN base addresses: |
92 | 28 | Michael Wallbank | <pre> |
93 | 29 | Michael Wallbank | Board Address |
94 | 8 | Michael Wallbank | 1742 3211 |
95 | 28 | Michael Wallbank | 2495 3210 |
96 | 8 | Michael Wallbank | 1495 0100 |
97 | 28 | Michael Wallbank | </pre> |
98 | 8 | Michael Wallbank | |
99 | 1 | Michael Wallbank | h2. V1742 Digitizer |
100 | 3 | Michael Wallbank | |
101 | 3 | Michael Wallbank | h3. Post-Trigger |
102 | 3 | Michael Wallbank | |
103 | 3 | Michael Wallbank | The V1742 has a register named @POST_TRIGGER@. This value is a percentage of the readout that is to be after the trigger. There is an implicit latency of around 40 ns, so in reality, the Post-Trigger percentage sets the percentage of the readout that will be *after* 40 ns past the trigger. |
104 | 3 | Michael Wallbank | |
105 | 3 | Michael Wallbank | For an unknown reason, only certain values of @POST_TRIGGER@ are accepted and must be found by trial and error. |
106 | 3 | Michael Wallbank | |
107 | 3 | Michael Wallbank | h3. Known working values |
108 | 3 | Michael Wallbank | |
109 | 3 | Michael Wallbank | * 0 |
110 | 3 | Michael Wallbank | * 20 |
111 | 3 | Michael Wallbank | * 45 |
112 | 4 | Michael Wallbank | |
113 | 9 | Michael Wallbank | h2. MWPC Controller(s) |
114 | 4 | Michael Wallbank | |
115 | 9 | Michael Wallbank | Beamline: |
116 | 9 | Michael Wallbank | * Hardware address: 00.80.55.00.00.68 |
117 | 9 | Michael Wallbank | * IP address: 131.225.176.70 |
118 | 1 | Michael Wallbank | * Name: ftbfwc03 |
119 | 1 | Michael Wallbank | * CD system reference number: S22041 |
120 | 1 | Michael Wallbank | * CD equipment ID number: 557912 |
121 | 1 | Michael Wallbank | |
122 | 9 | Michael Wallbank | Target: |
123 | 9 | Michael Wallbank | * Hardware address: 00.80.55.EE.00.08 |
124 | 9 | Michael Wallbank | * IP address: 131.225.176.164 |
125 | 9 | Michael Wallbank | * Name: ftbfwc07 |
126 | 9 | Michael Wallbank | * CD system reference number: S22056 |
127 | 9 | Michael Wallbank | |
128 | 9 | Michael Wallbank | Log in (e.g.): |
129 | 4 | Michael Wallbank | |
130 | 4 | Michael Wallbank | <pre> |
131 | 4 | Michael Wallbank | telnet ftbfwc03 <port> |
132 | 4 | Michael Wallbank | </pre> |
133 | 4 | Michael Wallbank | |
134 | 30 | Michael Wallbank | Ports: |
135 | 30 | Michael Wallbank | * 5000 - emergency access |
136 | 30 | Michael Wallbank | * 5001 - DAQ |
137 | 4 | Michael Wallbank | * 5002 - telnet sessions |
138 | 5 | Michael Wallbank | |
139 | 7 | Michael Wallbank | [[MWPC Configuration and Registers]] |