Front-end information » History » Version 23
Michael Wallbank, 07/01/2019 09:48 AM
1 | 1 | Michael Wallbank | h1. Front-end information |
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2 | 1 | Michael Wallbank | |
3 | 19 | Will Flanagan | h2. V1742/V1495 channel mapping (Last Modified: June 27 2019) |
4 | 1 | Michael Wallbank | |
5 | 12 | Varun Raj | <pre> |
6 | 22 | Michael Wallbank | Input | Digitizer Channel |
7 | 22 | Michael Wallbank | ---------------------------------+------------------- |
8 | 22 | Michael Wallbank | Cherenkov | 0 |
9 | 22 | Michael Wallbank | ToF DS 5 (SiPM) | 4 |
10 | 22 | Michael Wallbank | ToF DS 6 (SiPM) | 5 |
11 | 22 | Michael Wallbank | ToF DS 7 (SiPM) | 6 |
12 | 22 | Michael Wallbank | ToF DS 8 (SiPM) | 7 |
13 | 22 | Michael Wallbank | ToF US 1 (PMT) | 8 |
14 | 22 | Michael Wallbank | ToF US 2 (PMT) | 9 |
15 | 22 | Michael Wallbank | ToF US 3 (PMT) | 10 |
16 | 22 | Michael Wallbank | ToF US 4 (PMT) | 11 |
17 | 22 | Michael Wallbank | ToF DS 1 (PMT) | 12 |
18 | 22 | Michael Wallbank | ToF DS 2 (PMT) | 13 |
19 | 22 | Michael Wallbank | ToF DS 3 (PMT) | 14 |
20 | 22 | Michael Wallbank | ToF DS 4 (PMT) | 15 |
21 | 1 | Michael Wallbank | </pre> |
22 | 1 | Michael Wallbank | |
23 | 12 | Varun Raj | <pre> |
24 | 22 | Michael Wallbank | Input | Trigger Channel |
25 | 22 | Michael Wallbank | ---------------------------------+------------------- |
26 | 22 | Michael Wallbank | WC 1 Logic | 0 |
27 | 23 | Michael Wallbank | WC 2 Logic | 1 |
28 | 22 | Michael Wallbank | WC 3 Logic | 2 |
29 | 22 | Michael Wallbank | WC 4 Logic | 3 |
30 | 22 | Michael Wallbank | Scintillator Paddle 1 (Mock WC1) | 4 |
31 | 22 | Michael Wallbank | Scintillator Paddle 2 (Mock WC2) | 5 |
32 | 22 | Michael Wallbank | Scintillator Paddle 3 (Mock WC3) | 6 |
33 | 22 | Michael Wallbank | Scintillator Paddle 4 (Mock WC4) | 7 |
34 | 22 | Michael Wallbank | Readout Gate | 8 |
35 | 22 | Michael Wallbank | Switchyard Gate | 9 |
36 | 22 | Michael Wallbank | MWPC Off | 10 |
37 | 22 | Michael Wallbank | Digitizer Busy | 11 |
38 | 22 | Michael Wallbank | MWPC Coincidence | 12 |
39 | 22 | Michael Wallbank | EMPTY | 13 |
40 | 22 | Michael Wallbank | TOFPrompt Logic | 14 |
41 | 23 | Michael Wallbank | TOFSlow Logic | 15 |
42 | 12 | Varun Raj | </pre> |
43 | 10 | Michael Wallbank | |
44 | 8 | Michael Wallbank | h2. VME crate |
45 | 8 | Michael Wallbank | |
46 | 8 | Michael Wallbank | As user novadaq, the directory |
47 | 8 | Michael Wallbank | <pre> |
48 | 8 | Michael Wallbank | /home/nfs/novadaq/ |
49 | 8 | Michael Wallbank | </pre> |
50 | 8 | Michael Wallbank | on novabeamlinedaq00 contains some useful utilities to communicate with the hardware. All CAEN provided software. |
51 | 8 | Michael Wallbank | |
52 | 8 | Michael Wallbank | Run CAEN upgrader GUI: |
53 | 8 | Michael Wallbank | <pre> |
54 | 8 | Michael Wallbank | ./CAENUpgrader-1.6.3/CAENUpgraderGUI/CAENUpgraderGUI |
55 | 8 | Michael Wallbank | </pre> |
56 | 8 | Michael Wallbank | |
57 | 8 | Michael Wallbank | Run CAEN V1742 digitizer (outside of DAQ): |
58 | 8 | Michael Wallbank | <pre> |
59 | 8 | Michael Wallbank | wavedump-3.8.2/bin/wavedump /etc/wavedump/WaveDumpConfig_X742.txt |
60 | 8 | Michael Wallbank | </pre> |
61 | 8 | Michael Wallbank | |
62 | 8 | Michael Wallbank | Run CAEN VME module: |
63 | 8 | Michael Wallbank | <pre> |
64 | 8 | Michael Wallbank | ./CAENVMELib-2.50/sample/CAENVMEDemo V2718 <base address, in hex (beginning 0x)> <link> |
65 | 8 | Michael Wallbank | </pre> |
66 | 8 | Michael Wallbank | With this utilities, one can set the base address (option 2), set a register (option 1) and read etc. |
67 | 8 | Michael Wallbank | |
68 | 8 | Michael Wallbank | CAEN base addresses: |
69 | 8 | Michael Wallbank | Board Address |
70 | 8 | Michael Wallbank | 1742 3211 |
71 | 8 | Michael Wallbank | 2495 3210 |
72 | 8 | Michael Wallbank | 1495 0100 |
73 | 8 | Michael Wallbank | |
74 | 1 | Michael Wallbank | h2. V1742 Digitizer |
75 | 3 | Michael Wallbank | |
76 | 3 | Michael Wallbank | h3. Post-Trigger |
77 | 3 | Michael Wallbank | |
78 | 3 | Michael Wallbank | The V1742 has a register named @POST_TRIGGER@. This value is a percentage of the readout that is to be after the trigger. There is an implicit latency of around 40 ns, so in reality, the Post-Trigger percentage sets the percentage of the readout that will be *after* 40 ns past the trigger. |
79 | 3 | Michael Wallbank | |
80 | 3 | Michael Wallbank | For an unknown reason, only certain values of @POST_TRIGGER@ are accepted and must be found by trial and error. |
81 | 3 | Michael Wallbank | |
82 | 3 | Michael Wallbank | h3. Known working values |
83 | 3 | Michael Wallbank | |
84 | 3 | Michael Wallbank | * 0 |
85 | 3 | Michael Wallbank | * 20 |
86 | 3 | Michael Wallbank | * 45 |
87 | 4 | Michael Wallbank | |
88 | 9 | Michael Wallbank | h2. MWPC Controller(s) |
89 | 4 | Michael Wallbank | |
90 | 9 | Michael Wallbank | Beamline: |
91 | 9 | Michael Wallbank | * Hardware address: 00.80.55.00.00.68 |
92 | 9 | Michael Wallbank | * IP address: 131.225.176.70 |
93 | 1 | Michael Wallbank | * Name: ftbfwc03 |
94 | 1 | Michael Wallbank | * CD system reference number: S22041 |
95 | 1 | Michael Wallbank | * CD equipment ID number: 557912 |
96 | 1 | Michael Wallbank | |
97 | 9 | Michael Wallbank | Target: |
98 | 9 | Michael Wallbank | * Hardware address: 00.80.55.EE.00.08 |
99 | 9 | Michael Wallbank | * IP address: 131.225.176.164 |
100 | 9 | Michael Wallbank | * Name: ftbfwc07 |
101 | 9 | Michael Wallbank | * CD system reference number: S22056 |
102 | 9 | Michael Wallbank | |
103 | 9 | Michael Wallbank | Log in (e.g.): |
104 | 4 | Michael Wallbank | |
105 | 4 | Michael Wallbank | <pre> |
106 | 4 | Michael Wallbank | telnet ftbfwc03 <port> |
107 | 4 | Michael Wallbank | </pre> |
108 | 4 | Michael Wallbank | |
109 | 4 | Michael Wallbank | Ports (according to "here":https://cdcvs.fnal.gov/redmine/projects/ftbfwirechamberdaq/wiki/Wire_Chamber_DAQ_Developer) |
110 | 4 | Michael Wallbank | * 5000 - daq apps |
111 | 4 | Michael Wallbank | * 5001 - emergency access |
112 | 4 | Michael Wallbank | * 5002 - telnet sessions |
113 | 5 | Michael Wallbank | |
114 | 7 | Michael Wallbank | [[MWPC Configuration and Registers]] |