Project

General

Profile

Front-end information » History » Version 21

Michael Wallbank, 07/01/2019 09:45 AM

1 1 Michael Wallbank
h1. Front-end information
2 1 Michael Wallbank
3 19 Will Flanagan
h2. V1742/V1495 channel mapping (Last Modified: June 27 2019)
4 1 Michael Wallbank
5 12 Varun Raj
<pre>
6 12 Varun Raj
Input                            | Digitizer Channel | Trigger Channel 
7 12 Varun Raj
---------------------------------+-------------------+------------------
8 17 Aidan Medcalf
Cherenkov                        | 0                 | NC
9 16 Aidan Medcalf
ToF DS 5 (SiPM)                  | 4                 | NC
10 16 Aidan Medcalf
ToF DS 6 (SiPM)                  | 5                 | NC
11 16 Aidan Medcalf
ToF DS 7 (SiPM)                  | 6                 | NC
12 16 Aidan Medcalf
ToF DS 8 (SiPM)                  | 7                 | NC
13 12 Varun Raj
ToF US 1 (PMT)                   | 8                 | NC 
14 12 Varun Raj
ToF US 2 (PMT)                   | 9                 | NC
15 12 Varun Raj
ToF US 3 (PMT)                   | 10                | NC
16 12 Varun Raj
ToF US 4 (PMT)                   | 11                | NC
17 1 Michael Wallbank
ToF DS 1 (PMT)                   | 12                | NC
18 1 Michael Wallbank
ToF DS 2 (PMT)                   | 13                | NC
19 1 Michael Wallbank
ToF DS 3 (PMT)                   | 14                | NC
20 12 Varun Raj
ToF DS 4 (PMT)                   | 15                | NC
21 21 Michael Wallbank
</pre>
22 21 Michael Wallbank
23 21 Michael Wallbank
<pre>
24 1 Michael Wallbank
WC 1 Logic                       | NC                | 0
25 1 Michael Wallbank
WC 2 Logic                       | NC                | 1
26 1 Michael Wallbank
WC 3 Logic                       | NC                | 2
27 1 Michael Wallbank
WC 4 Logic                       | NC                | 3
28 21 Michael Wallbank
Scintillator Paddle 1 (Mock WC1) | NC                | 4
29 21 Michael Wallbank
Scintillator Paddle 2 (Mock WC2) | NC                | 5
30 21 Michael Wallbank
Scintillator Paddle 3 (Mock WC3) | NC                | 6
31 21 Michael Wallbank
Scintillator Paddle 4 (Mock WC4) | NC                | 7
32 20 Michael Wallbank
Readout Gate                     | NC                | 8
33 20 Michael Wallbank
Switchyard Gate                  | NC                | 9
34 20 Michael Wallbank
MWPC Off                         | NC                | 10
35 20 Michael Wallbank
Digitizer Busy                   | NC                | 11
36 20 Michael Wallbank
MWPC Coincidence                 | NC                | 12
37 18 Will Flanagan
TOFPrompt Logic                  | NC                | 14
38 18 Will Flanagan
TOFSlow Logic                    | NC                | 15
39 12 Varun Raj
</pre>
40 10 Michael Wallbank
41 8 Michael Wallbank
h2. VME crate
42 8 Michael Wallbank
43 8 Michael Wallbank
As user novadaq, the directory
44 8 Michael Wallbank
<pre>
45 8 Michael Wallbank
/home/nfs/novadaq/
46 8 Michael Wallbank
</pre>
47 8 Michael Wallbank
on novabeamlinedaq00 contains some useful utilities to communicate with the hardware.  All CAEN provided software.
48 8 Michael Wallbank
49 8 Michael Wallbank
Run CAEN upgrader GUI:
50 8 Michael Wallbank
<pre>
51 8 Michael Wallbank
./CAENUpgrader-1.6.3/CAENUpgraderGUI/CAENUpgraderGUI
52 8 Michael Wallbank
</pre>
53 8 Michael Wallbank
54 8 Michael Wallbank
Run CAEN V1742 digitizer (outside of DAQ):
55 8 Michael Wallbank
<pre>
56 8 Michael Wallbank
wavedump-3.8.2/bin/wavedump /etc/wavedump/WaveDumpConfig_X742.txt
57 8 Michael Wallbank
</pre>
58 8 Michael Wallbank
59 8 Michael Wallbank
Run CAEN VME module:
60 8 Michael Wallbank
<pre>
61 8 Michael Wallbank
./CAENVMELib-2.50/sample/CAENVMEDemo V2718 <base address, in hex (beginning 0x)> <link>
62 8 Michael Wallbank
</pre>
63 8 Michael Wallbank
With this utilities, one can set the base address (option 2), set a register (option 1) and read etc.
64 8 Michael Wallbank
65 8 Michael Wallbank
CAEN base addresses:
66 8 Michael Wallbank
Board     Address
67 8 Michael Wallbank
1742       3211
68 8 Michael Wallbank
2495      3210
69 8 Michael Wallbank
1495       0100
70 8 Michael Wallbank
71 1 Michael Wallbank
h2. V1742 Digitizer
72 3 Michael Wallbank
73 3 Michael Wallbank
h3. Post-Trigger
74 3 Michael Wallbank
75 3 Michael Wallbank
The V1742 has a register named @POST_TRIGGER@. This value is a percentage of the readout that is to be after the trigger. There is an implicit latency of around 40 ns, so in reality, the Post-Trigger percentage sets the percentage of the readout that will be *after* 40 ns past the trigger.
76 3 Michael Wallbank
77 3 Michael Wallbank
For an unknown reason, only certain values of @POST_TRIGGER@ are accepted and must be found by trial and error.
78 3 Michael Wallbank
79 3 Michael Wallbank
h3. Known working values
80 3 Michael Wallbank
81 3 Michael Wallbank
* 0
82 3 Michael Wallbank
* 20
83 3 Michael Wallbank
* 45
84 4 Michael Wallbank
85 9 Michael Wallbank
h2. MWPC Controller(s)
86 4 Michael Wallbank
87 9 Michael Wallbank
Beamline:
88 9 Michael Wallbank
* Hardware address: 00.80.55.00.00.68
89 9 Michael Wallbank
* IP address: 131.225.176.70
90 1 Michael Wallbank
* Name: ftbfwc03
91 1 Michael Wallbank
* CD system reference number: S22041
92 1 Michael Wallbank
* CD equipment ID number: 557912
93 1 Michael Wallbank
94 9 Michael Wallbank
Target:
95 9 Michael Wallbank
* Hardware address: 00.80.55.EE.00.08
96 9 Michael Wallbank
* IP address: 131.225.176.164
97 9 Michael Wallbank
* Name: ftbfwc07
98 9 Michael Wallbank
* CD system reference number: S22056
99 9 Michael Wallbank
100 9 Michael Wallbank
Log in (e.g.):
101 4 Michael Wallbank
102 4 Michael Wallbank
<pre>
103 4 Michael Wallbank
telnet ftbfwc03 <port>
104 4 Michael Wallbank
</pre>
105 4 Michael Wallbank
106 4 Michael Wallbank
Ports (according to "here":https://cdcvs.fnal.gov/redmine/projects/ftbfwirechamberdaq/wiki/Wire_Chamber_DAQ_Developer)
107 4 Michael Wallbank
* 5000 - daq apps
108 4 Michael Wallbank
* 5001 - emergency access
109 4 Michael Wallbank
* 5002 - telnet sessions
110 5 Michael Wallbank
111 7 Michael Wallbank
[[MWPC Configuration and Registers]]