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Michael Wallbank, 07/01/2019 09:42 AM

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h1. Front-end information
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h2. V1742/V1495 channel mapping (Last Modified: June 27 2019)
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<pre>
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Input                            | Digitizer Channel | Trigger Channel 
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---------------------------------+-------------------+------------------
8 17 Aidan Medcalf
Cherenkov                        | 0                 | NC
9 14 Aidan Medcalf
Scintillator Paddle 1 (Mock WC1) | NC                | 4
10 14 Aidan Medcalf
Scintillator Paddle 2 (Mock WC2) | NC                | 5
11 14 Aidan Medcalf
Scintillator Paddle 3 (Mock WC3) | NC                | 6
12 14 Aidan Medcalf
Scintillator Paddle 4 (Mock WC4) | NC                | 7
13 16 Aidan Medcalf
ToF DS 5 (SiPM)                  | 4                 | NC
14 16 Aidan Medcalf
ToF DS 6 (SiPM)                  | 5                 | NC
15 16 Aidan Medcalf
ToF DS 7 (SiPM)                  | 6                 | NC
16 16 Aidan Medcalf
ToF DS 8 (SiPM)                  | 7                 | NC
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ToF US 1 (PMT)                   | 8                 | NC 
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ToF US 2 (PMT)                   | 9                 | NC
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ToF US 3 (PMT)                   | 10                | NC
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ToF US 4 (PMT)                   | 11                | NC
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ToF DS 1 (PMT)                   | 12                | NC
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ToF DS 2 (PMT)                   | 13                | NC
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ToF DS 3 (PMT)                   | 14                | NC
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ToF DS 4 (PMT)                   | 15                | NC
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WC 1 Logic                       | NC                | 0
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WC 2 Logic                       | NC                | 1
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WC 3 Logic                       | NC                | 2
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WC 4 Logic                       | NC                | 3
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Readout Gate                     | NC                | 8
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Switchyard Gate                  | NC                | 9
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MWPC Off                         | NC                | 10
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Digitizer Busy                   | NC                | 11
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MWPC Coincidence                 | NC                | 12
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TOFPrompt Logic                  | NC                | 14
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TOFSlow Logic                    | NC                | 15
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</pre>
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h2. VME crate
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As user novadaq, the directory
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<pre>
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/home/nfs/novadaq/
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</pre>
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on novabeamlinedaq00 contains some useful utilities to communicate with the hardware.  All CAEN provided software.
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Run CAEN upgrader GUI:
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<pre>
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./CAENUpgrader-1.6.3/CAENUpgraderGUI/CAENUpgraderGUI
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</pre>
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Run CAEN V1742 digitizer (outside of DAQ):
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<pre>
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wavedump-3.8.2/bin/wavedump /etc/wavedump/WaveDumpConfig_X742.txt
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</pre>
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Run CAEN VME module:
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<pre>
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./CAENVMELib-2.50/sample/CAENVMEDemo V2718 <base address, in hex (beginning 0x)> <link>
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</pre>
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With this utilities, one can set the base address (option 2), set a register (option 1) and read etc.
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CAEN base addresses:
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Board     Address
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1742       3211
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2495      3210
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1495       0100
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h2. V1742 Digitizer
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h3. Post-Trigger
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The V1742 has a register named @POST_TRIGGER@. This value is a percentage of the readout that is to be after the trigger. There is an implicit latency of around 40 ns, so in reality, the Post-Trigger percentage sets the percentage of the readout that will be *after* 40 ns past the trigger.
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For an unknown reason, only certain values of @POST_TRIGGER@ are accepted and must be found by trial and error.
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h3. Known working values
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* 0
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* 20
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* 45
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h2. MWPC Controller(s)
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Beamline:
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* Hardware address: 00.80.55.00.00.68
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* IP address: 131.225.176.70
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* Name: ftbfwc03
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* CD system reference number: S22041
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* CD equipment ID number: 557912
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Target:
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* Hardware address: 00.80.55.EE.00.08
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* IP address: 131.225.176.164
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* Name: ftbfwc07
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* CD system reference number: S22056
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Log in (e.g.):
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<pre>
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telnet ftbfwc03 <port>
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</pre>
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Ports (according to "here":https://cdcvs.fnal.gov/redmine/projects/ftbfwirechamberdaq/wiki/Wire_Chamber_DAQ_Developer)
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* 5000 - daq apps
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* 5001 - emergency access
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* 5002 - telnet sessions
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[[MWPC Configuration and Registers]]