Front-end information¶
V1742/V1495 channel mapping (Last Modified: July 1 2019)¶
Input | Digitizer Channel ---------------------------------+------------------- Cherenkov | 0 ToF DS 5 (SiPM) | 4 ToF DS 6 (SiPM) | 5 ToF DS 7 (SiPM) | 6 ToF DS 8 (SiPM) | 7 ToF US 1 (PMT) | 8 ToF US 2 (PMT) | 9 ToF US 3 (PMT) | 10 ToF US 4 (PMT) | 11 ToF DS 1 (PMT) | 12 ToF DS 2 (PMT) | 13 ToF DS 3 (PMT) | 14 ToF DS 4 (PMT) | 15
Input | Trigger Channel | Description
---------------------------------+--------------------+----------------------------------------------------------------------------
WC 1 Logic | 0 | Wire chamber 1 (X|X & Y|Y) (40ns) -- First four trigger board inputs have additional M of 4 logic, M = {1,2,3,4}
WC 2 Logic | 1 | Wire chamber 2 (X|X & Y|Y) (40ns)
WC 3 Logic | 2 | Wire chamber 3 (X|X & Y|Y) (40ns)
WC 4 Logic | 3 | Wire chamber 4 (X|X & Y|Y) (40ns)
Scintillator Paddle 1 (Mock WC1) | 4 | Pad 1 at position of WC1
Scintillator Paddle 2 (Mock WC2) | 5 | Pad 2 at position of WC2
Scintillator Paddle 3 (Mock WC3) | 6 | Pad 3 at position of WC3
Scintillator Paddle 4 (Mock WC4) | 7 | Pad 4 at position of WC4
Readout Gate | 8 | $00 -> $00+T DAQ readout window (T ~ 40s)
Switchyard Gate | 9 | $30 -> $36 gate; same readout gate as the MWPC Controller
MWPC Off | 10 | Readout inhibit: TRUE when MWPC Controller is available to accept a new trigger (10us gate)
Digitizer Busy | 11 | Readout inhibit: TRUE when the digitizer is done digitizing previous triggers (~O(100us))
WC Hardware Coincidence | 12 | Wire chamber trigger logic done in NIM bin; 30ns outputs for TDCs 2,3,4 (2 of 3 coincidence) in AND coincidence with 10ns output for TDC 1; see diagram below
EMPTY | 13 |
TOFPrompt Logic | 14 | Time-of-flight prompt trigger signal; 10ns DS ToF in coincidence in 65ns-delayed 10ns US ToF (fast particle ToF ~ 44ns); see diagram below
TOFSlow Logic | 15 | Time-of-flight slow trigger signal; 10ns DS ToF in coincidence in 75ns-delayed 90ns US ToF (slow particle ToF > 44ns); see diagram below
New proposed trigger board configuration:
Input | Trigger Channel ---------------------------------+------------------- WC 1 Logic | 0 WC 2 Logic | 1 WC 3 Logic | 2 WC 4 Logic | 3 Scintillator Paddle 1 (Mock WC1) | 4 Scintillator Paddle 2 (Mock WC2) | 5 Scintillator Paddle 3 (Mock WC3) | 6 Scintillator Paddle 4 (Mock WC4) | 7 TOF US | 8 Switchyard Gate | 9 MWPC Off | 10 Digitizer Busy | 11 MWPC Coincidence | 12 TOF DS | 13 TOFPrompt Logic | 14 TOFSlow Logic | 15
VME crate¶
As user novadaq, the directory
/home/nfs/novadaq/
on novabeamlinedaq00 contains some useful utilities to communicate with the hardware. All CAEN provided software.
Run CAEN upgrader GUI:
./CAENUpgrader-1.6.3/CAENUpgraderGUI/CAENUpgraderGUI
Run CAEN V1742 digitizer (outside of DAQ):
wavedump-3.8.2/bin/wavedump /etc/wavedump/WaveDumpConfig_X742.txt
Run CAEN VME module:
./CAENVMELib-2.50/sample/CAENVMEDemo V2718 <base address, in hex (beginning 0x)> <link>
With this utilities, one can set the base address (option 2), set a register (option 1) and read etc.
CAEN base addresses:
Board Address 1742 3211 2495 3210 1495 0100
V1742 Digitizer¶
Post-Trigger¶
The V1742 has a register named POST_TRIGGER. This value is a percentage of the readout that is to be after the trigger. There is an implicit latency of around 40 ns, so in reality, the Post-Trigger percentage sets the percentage of the readout that will be after 40 ns past the trigger.
For an unknown reason, only certain values of POST_TRIGGER are accepted and must be found by trial and error.
Known working values¶
- 0
- 20
- 45
MWPC Controller(s)¶
Beamline:- Hardware address: 00.80.55.00.00.68
- IP address: 131.225.176.70
- Name: ftbfwc03
- CD system reference number: S22041
- CD equipment ID number: 557912
- Hardware address: 00.80.55.EE.00.08
- IP address: 131.225.176.164
- Name: ftbfwc07
- CD system reference number: S22056
Log in (e.g.):
telnet ftbfwc03 <port>Ports:
- 5000 - emergency access
- 5001 - DAQ
- 5002 - telnet sessions