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General

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17-Jan-2019

Agenda:
1. General status updates/Schedule review
2. Timing distribution status (DCS reads and writes?)
3. online Trigger Processing (including through DTC) progress/plans
4. Status of tests with detector subsystems
5. Rack protection & slow controls progress/plans

Jose -- working on dynamic phase shift through DCS commands. And counter for loss lock.

Rick -- Link 1 problem should be fixed. CRV brought setup over yesterday.. They were having errors.. But they didnt have the DTC fan solution -- Added the fan. Another CRV, gets errors have 1000s of events… added a watchdog to watch for it going full. Looking at 1000 read hanging… ots was not restarting..

Tomo -- updating packet generating and parsing modules to include the CRV format.. It has per event status packets.

Glenn -- rack monitor slow controls box.. Dave had two assembled ones. Glenn likes the BeagleBone mother board.. Easy to access. Wants to hardcode identity on the memory. There is also an i2c prom for serial number uniquely IDing the board. Has 6 temperature probe ports.

FPGA CRR -- 48 hour burn in and test DMA/PCIe.. And loopback.. 2m firefly.. And test

Greg and Ryan met with Gary -- we showed him the 250ps precise loopback.. The loopback changes from lock to lock.. We are establishing procedure to handle that -- how do we minimize dead time?

Three loopback modes at ROC: Baseline, Baseline+Coarse, Baseline+Coarse+Fine.