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16-Aug-2018

Eric -- CRV people are still here trying to debug HW issues. Rick has new code that needs an interface I2C

Rick -- CRV test works in Rick’s office but not in open bay. Made a version with more chipscopes. Asking for multiple data blocks, only one packet makes it through DTC. Trying to get Ethan’s to place and route with chipscope in it. Timing distribution for 2 DTCs requires a software change.

Ethan -- finishing up firmware trigger, and eager to start debugging. 4 weeks left

Jose -- working on timing synch demonstration with polar fire.

Tomo -- updated online code to use lastest packet format. So simulation data has latest packets, and is running them through processing chain. Using an old branch though that’s compatible with artdaq, which prevents filter matching. Modified offline to test how much gain we get from preprocessing information.

Bertrand -- just back from vacation. We should discuss Ethan’s exit plan.

Request for new mu2e artdaq online.

Ryan -- working with Jose and Ethan. And understanding FPGA CRR.