Project

General

Profile

02-Aug-2018

1. General status updates/Schedule review
Rick -- testing new timing card. It powers up.. Trying to program jitter attenuator. Trying place and route soon.. Trying separate route of Ethan’s block. Helping Jose also. How do we want run the playback through the filter?

Eric -- CRV team says they are happy with progress talking to DTC. CRV representatives are coming next week to take their system. Dedicated DCS machine will be DAQ03.. Process started to reinstall, reconfigure, and rename. We should setup the timing sync test -- possibly 1 CFO & 2 DTCs in one node.

Tomo -- Updated data packet specification - included point to point topology and adds preprocessing flags. Tracker is now 15 samples instead of 16 samples. Calorimeter is going to do some preprocessing in their ROC. Working with Rob on the Mock-data challenge, to simulate data blocks converted into artdaq fragments. Will send (possibly broken) full node utilization tests to Ron. We have not run a timing benchmark assuming the preprocessing flags are there.

Ron -- What is event building status? (Rick says we need to revisit, Ryan says put on backburner)

Jose -- Now receiving from the VTRx .. it inverts the serial bitstream!! Xilinx can software configure inversion on the fly. Next working on synchronizing ROC 40MHz clock to 40MHz marker.

Greg -- Had conversations with Vadim and Sten about event window width, and looks like we can proceed as planned. Interesting issue transitioning from OFF-Spill to ON-Spill (“PRE-Spill”)

Ethan -- finished preprocessing example and gave vhdl to Rick.

Glenn -- posted wiki instructions for how to run DCS on 04.. And is prepared for 03 move.

Ryan --Submitted change request. Think about slowing down charging pace.