1. General status updates/Schedule
Bertrand - good news! Dave Brown found way to increase resolution and decrease occupancy. Considering clusters of 2 a single hit, lowers occupancy to 60%. (need geometry and calibration constants). We are still getting an idea of timing. Russian students interested in working with FPGA trigger algorithm.
Tomo - offline was missing key things/bug. Now online needs to update to new fixes in offline. Shifting attention to FPGA development. Vivado/Xilinx High Level Synthesis C++ to VHDL.
Eric - trying to get artdaq to support the latest version of art (art has changed key things, possibly broke them). Do we need to Rob and Bertrand to complain? Artdaq v3 will be needed, and Mu2e artdaq will need to be updated to that.
Rick - working on vertical slice.. Can send Request test data packets to CRV and get data packets back! Also working with DRAC and Vadim.. Running at 2.5Gbps right now (Tracker using old Tracker ROC prototype code). Keeps unlocking .. probably because SF2 is using internal clock. In the mean time looking at CFO and 10G link. DTC 10G with and roc links has some bugs. Jose sent some notes.
We ordered non rad hard fiber $1K.
Struggling to get online algorithm timing benchmark
Firmware seems to be in good shape
We think we will have to redesign the timing distribution card because of VRTx (we need to synchronize transmit links with a single source clock)
Should submit change request.
Extra firmware release to accomodate
Check on DCS switches.
Glenn - Needs help with someone connecting BeagleBone black. Not much progress on getting EPICS
2. Timing distribution updates
3. online Trigger Processing (including through DTC) progress/plans (highest priority)
4. Status of tests with detector subystems
5. Rack protection & slow controls progress/plans