LBL Low Level RF System¶

Introduction:
This project involves implementing the Low Level RF Control system for PIP2 IT SSR1. The HW/FW/SW are heavily borrowed from the LCLS-II LLRF System, with some important differences: while the same resonance control chassis will be used, the PIP2 architecture differs in that a new LBL LLRF Controller chassis has been developed that contains the Zest digitzer board as well as its mating QF2-pre FPGA board (this same board is used in resonance control chassis). The LBL LLRF system uses EPICS software for its control and operation. In LCLS-II the system architecture split the functions between PRC (Downconverter + ADC/DAC board + FPGA board) which streamed digitized data via fiber to the LLRF Controller (which ran the LLRF algorithm). For PIP-II the data converter + FPGA board are in one chassis, and a single FPGA handles the data conversion as well as runs the LLRF algorithm. RF frequency conversion to/from IF (20MHz) is handled by FNAL Up/Down Converter Chassis; these are purely analog units.

The initial application will be for the PIP2 IT Single Spoke Resonator 1 (SSR1) LLRF control. The RF frequency is 325MHz. SSR1 will serve as a demonstration platform for the LBL LLRF system applied to PIP2 and is part of the downselection process.

Note on nomenclature: For reference (and also because its cooked into the SW) the HW units were given specific names in LCLS-II:
RFS = RF Station (LLRF Controller)
RES = Resonance Controller
PRC = Precision Receiver Chassis (not used in PIP2 system)

This Redmine project and wiki page have been set up as a collection point for the project as well as for tracking of all of the tasks associated with it.

Working project areas:

• Y:\Projects\LLRF\Systems\LBL_LLRF (main folder)
• Y:\Projects\LLRF\Systems\LBL_LLRF\lbl_llrf_chassis (chassis and related system info is here)

System IP and MAC Addresses:¶

Device: Resonance Control Chassis / s/n = 1805173 (SLAC ID #)
Location: TGC LLRF Lab

• IP Address = 192.168.165.16
• MAC Address = 00:80:55:BD:04:20

Device: LLRF Controller Chassis (1U unit) / s/n = 289

• IP Address = 192.168.165.17
• MAC Address = 00:80:55:BD:04:21

Reference Documentation:¶

LCLS2 Paper: lcls2_llrf_paper.pdf
LCLS2 Paper: lcls2_llrf_paper.pdf
LCLS2 LLRF FDR Slides: FDR.pdf
LCLS2 Design Report: LCLS2_design_report.pdf
LCLS2 Paper: lcls2_llrf_paper.pdf

System Documentation:¶

System-Level Documents:

• Overall System Diagram: <to be created> (to describe complete system from the cavity to the fibers)
• Fiber Interconnect Diagram: <to be created>
• System Design Specification: <to be created>
• System Interface Control Document: <to be created>

PIP2 LBL LLRF Controller:¶

QF2-pre FPGA Board:
This mates with the ZEST ADC/DAC FMC board in the controller as well as with the support electronics in the resonance control chassis

• qf2-pre Manual: QF2-pre_Guide.pdf
  Python Utils: Needed to set the MAC & IP addresses!
• Python Board Utils (Res Ctrlr version): qf2-pre-users-lcls2.zip
• Python Board Utils (LLRF Ctrlr version): qf2-pre-users-master.zip
• Note on programming the QF2-pre: QF2-pre_programming_note.docx
• Console Logfile from setup of Res Ctrl chassis: lab_res_ctrlr_setup_log.txt (all the commands entered to set the IP)
• Console Logfile from setup of LLRF chassis: lab_LLRF_ctrlr_setup_log.txt (all the commands entered to set the IP)

LLRF 1u Chassis:
The LBL LLRF Controller is housed in a Supermicros Model SC515 1U Server Chassis:

• Chassis Datasheet: SC515.pdf
• Chassis IPMI Controller: impi_controller_board_CSE-PTJBOD-CB3.pdf

LLRF Firmware:
Using the LCLS2 FEED FW, but with mods for PIP2

• PIP2 FW: PIP-II_LLRF_Firmware.pptx

Resonance Control Chassis:
Using the LCLS2 version to start with, the JLab Version will replace it for production PIP2

• <Documents to be added....>

Fiber Optic Components & Patch Panel:
Using the LCLS2 version to start with, the JLab Version will replace it for production PIP2

• LCLS2 Fiber Patch Panel Diagram: LCLS2_LLRF_fiber_patch_panel.pdf
• LCLS2 Fiber Patch Panel Diagram: LCLS2_LLRF_fiber_patch_panel.vsdx
• LCLS2 Fiber Patch Panel Design Dwb: LLRF_fiber_chassis_to_network.vsd
• LCLS2 Fiber Mapping: SLAC_InternalMapping081120.pdf

Analog Cavity Emulator:
Just a collection of information, plus a preliminary design sketch

FNAL Ideas:

• Preliminary Design Sketch (vision source):analog_RF_cavity_emulator.vsd
• Preliminary Design Sketch (with notes):design_sketch_with_notes.pdf

• Jlab slides:allison_15Oct09.pdf (Contains design & test results of their analog emulator, plus info on digital design)

SLAC Design:

• Design pt1: lowQ_cavity_emulator.pdf
• Design pt2: cavity_for_emulator.pdf
• Design pt3: emulator_for_housing.pdf
• Design Notes 1: SLAC_note_and_meas.docx
• Design Notes 2: SLAC_cav_emu_design_and_meas.docx

Reference Docs: (analog & digital emulators)

• Xtal Filter Spec App Note: HowtoSpecifyCrystalFilters.pdf
• Xtal Filter Tutorial: xtal_filter_tutorial.pdf
• article: article_10_1_1_66_5383.pdf
• article: article_1806_09268.pdf
• article: article_08405234.pdf
• article: PhysRevAccelBeams_21_032003.pdf

EPICS SW:
LLRF-specific EPICS Stuff:

• CMTS LCLS-II SW User Guide (Setup & User Guide): CMTS_LCLS-II_LLRF_Engineer_Software_Guide.pdf (Good -- start with this one)

• LERF RF SW User Guide (Setup & User Guide): LERF_RF_User_Guide.pdf (similar to above)

• EPICS & Console Screehshots (some pix of first running of PIP2 implementation, has EDM run command): EPICS_panel_screenshots.pdf