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John Dusatko, 09/18/2020 09:56 AM

LBL Low Level RF System

This project involves implementing the Low Level RF Control system for PIP2 IT SSR1. The HW/FW/SW are heavily borrowed from the LCLS-II LLRF System, with some important differences: while the same resonance control chassis will be used, the PIP2 architecture differs in that a new LBL LLRF Controller chassis has been developed that contains the Zest digitzer board as well as its mating QF2-pre FPGA board (this same board is used in resonance control chassis). The LBL LLRF system uses EPICS software for its control and operation. In LCLS-II the system architecture split the functions between PRC (Downconverter + ADC/DAC board + FPGA board) which streamed digitized data via fiber to the LLRF Controller (which ran the LLRF algorithm). For PIP-II the data converter + FPGA board are in one chassis, and a single FPGA handles the data conversion as well as runs the LLRF algorithm. RF frequency conversion to/from IF (20MHz) is handled by FNAL Up/Down Converter Chassis; these are purely analog units.

The initial application will be for the PIP2 IT Single Spoke Resonator 1 (SSR1) LLRF control. The RF frequency is 325MHz. SSR1 will serve as a demonstration platform for the LBL LLRF system applied to PIP2 and is part of the downselection process.

Note on nomenclature: For reference (and also because its cooked into the SW) the HW units were given specific names in LCLS-II:
RFS = RF Station (LLRF Controller)
RES = Resonance Controller
PRC = Precision Receiver Chassis (not used in PIP2 system)

This Redmine project and wiki page have been set up as a collection point for the project as well as for tracking of all of the tasks associated with it.

Working project areas:
  • Y:\Projects\LLRF\Systems\LBL_LLRF (main folder)
  • Y:\Projects\LLRF\Systems\LBL_LLRF\lbl_llrf_chassis (chassis and related system info is here)

System IP and MAC Addresses:

Device: Resonance Control Chassis / s/n = 1805173 (SLAC ID #)
Location: TGC LLRF Lab
  • IP Address =
  • MAC Address = 00:80:55:BD:04:20
Device: LLRF Controller Chassis (1U unit) / s/n = 289
  • IP Address =
  • MAC Address = 00:80:55:BD:04:21

Reference Documentation:

LCLS2 Paper: lcls2_llrf_paper.pdf
LCLS2 Paper: lcls2_llrf_paper.pdf
LCLS2 LLRF FDR Slides: FDR.pdf
LCLS2 Design Report: LCLS2_design_report.pdf
LCLS2 Paper: lcls2_llrf_paper.pdf

System Documentation:

System-Level Documents:
  • Overall System Diagram: <to be created> (to describe complete system from the cavity to the fibers)
  • Fiber Interconnect Diagram: <to be created>
  • System Design Specification: <to be created>
  • System Interface Control Document: <to be created>

PIP2 LBL LLRF Controller:

QF2-pre FPGA Board:
This mates with the ZEST ADC/DAC FMC board in the controller as well as with the support electronics in the resonance control chassis

LLRF 1u Chassis:
The LBL LLRF Controller is housed in a Supermicros Model SC515 1U Server Chassis:

LLRF Firmware:
Using the LCLS2 FEED FW, but with mods for PIP2

Resonance Control Chassis:
Using the LCLS2 version to start with, the JLab Version will replace it for production PIP2

  • <Documents to be added....>

Fiber Optic Components & Patch Panel:
Using the LCLS2 version to start with, the JLab Version will replace it for production PIP2

Analog Cavity Emulator:
Just a collection of information, plus a preliminary design sketch

FNAL Ideas:
  • Preliminary Design Sketch (vision source):analog_RF_cavity_emulator.vsd
  • Preliminary Design Sketch (with notes):design_sketch_with_notes.pdf
  • Jlab slides:allison_15Oct09.pdf (Contains design & test results of their analog emulator, plus info on digital design)

SLAC Design:

Reference Docs: (analog & digital emulators)

LLRF-specific EPICS Stuff: