Communicating with the wire chambers » History » Version 15
« Previous -
Version 15/28
(diff) -
Next » -
Current version
Will Flanagan, 08/30/2014 05:23 PM
Communicating with the wire chambers¶
Running the Wire Chamber Mini-DAQ¶
setup ftbf
cd ~ftbf_user/experiments/mc7
Look in instructions.txt
When you have a few seconds before a spill (in case you want to type a comment before you start the run)
./daq-mc7.py
Example comment: Good beam 32 GeV, 100 A. 2.5E+05 at MC7SC1
This daq fills one data file, appending each spill, until the user stops it.
Looking at the data, Beam Study¶
ssh ftbflx01
setup cern
cd ~ftbf_user/experiments/mc7/TkRec
paw
exec runtk
How to do a hard reboot of the WC¶
If the wire chamber controller at ftbfwc02 starts refusing connections it may need a reboot:
- from a browser go to http://ftbf-pdu00.fnal.gov
- User: admin Password: <on the board in the CR>
- Navigate to this screen:
- click on "Outlet 6" and then choose "Immediate Reboot" from the menu at the top
- The state will change to "Off" but will be pending. Wait a little while and refresh the screen or log back in. The WC should be back on.
If the problem persists, Instead do a hard reset of the controller from the telnet interface:
- telnet ftbfwc02.fnal.gov 5000
- FF
The telnet interface¶
This is experts only!
- telnet ftbfwc02.fnal.gov 5000
- also 5001 - 5003 are available
- "help" prints the top level help menu. h1,h2,h3 also print help menus
- "p0" gives a synopsis of the last spill, like so:
p0
Controllers Spill Data Header (5653mS SpillGate)
TotalWrdCnt = 00009F89 (40841 D)
SpillCounter = 00000001 (1 D)
RTC Year/Mon = E08 (14/08)
RTC Day/Hr = C0F (12/15)
RTC Min/Sec = F14 (15/20)
Trigger Cnt = 00000110
Status Bits = 0
Link Status = 0
TDC Spill Hdrs (1 <= 16)
Input Words TDCnum TrgCnt Status
1 00000A9E 0001 00000110 0008
2 00000A05 0002 00000110 0008
3 00000A2E 0003 00000110 0008
4 00000A22 0004 00000110 0008
5 000009D2 0005 00000110 0008
6 00000A89 0006 00000110 0008
7 000009E0 0007 00000110 0008
8 00000A32 0008 00000110 0008
9 000009D3 0009 00000110 0008
10 000009C8 000A 00000110 0008
11 000009D3 000B 00000110 0008
12 000009B0 000C 00000110 0008
13 000009C2 000D 00000110 0008
14 000009CE 000E 00000110 0008
15 000009B9 000F 00000110 0008
16 000009B8 0010 00000110 0008
- "hc n string" with n=1-16 writes string to TDC n. If n=0 then all TDCs are written to.
- "hc 0 rdi 0" writes the command "rdi 0" to all TDCS.
- The rdi command is documented in the help menu: RDI adr c Read/and Incr FPGA Addr(H), c=WrdCnt(D)
- The output is:
hc 0 rdi 0 7 27 ac a0 ffff ffff ffff ffff 380 380 380 380 380 380 380 380 7 27 ac a0 ffff ffff ffff ffff 380 380 380 380 380 380 380 380 7 27 ac a0 ffff ffff ffff ffff 380 380 380 380 380 380 380 380 7 27 ac a0 ffff ffff ffff ffff 380 380 380 380 380 380 380 380 7 27 ac a0 ffff ffff ffff ffff 380 380 380 380 380 380 380 380 7 27 ac a0 ffff ffff ffff ffff 380 380 380 380 380 380 380 380 7 27 ac a0 ffff ffff ffff ffff 380 380 380 380 380 380 380 380 7 27 ac a0 ffff ffff ffff ffff 380 380 380 380 380 380 380 380 7 27 ac a0 ffff ffff ffff ffff 380 380 380 380 380 380 380 380 7 27 ac a0 ffff ffff ffff ffff 380 380 380 380 380 380 380 380 7 27 ac a0 ffff ffff ffff ffff 380 380 380 380 380 380 380 380 7 27 ac a0 ffff ffff ffff ffff 380 380 380 380 380 380 380 380 7 27 ac a0 ffff ffff ffff ffff 380 380 380 380 380 380 380 380 7 27 ac a0 ffff ffff ffff ffff 380 380 380 380 380 380 380 380 7 27 ac a0 ffff ffff ffff ffff 380 380 380 380 380 380 380 380 7 27 ac a0 ffff ffff ffff ffff 380 380 380 380 380 380 380 380
- The rows of this readout correspond to the different TDCs.
- The columns of this readout have a well defined meaning. They correspond to registers in the "FTBF TDC FPGA Register Map" document found at TDC Readout Documentation. For example:
- The first column is the Control and status register - 0x00.
- The second is the gate width register - 0x01.
- The third is the time stamp counter initial value (a.k.a. clock adjust) - 0x03.
- The forth column is the Hit Pipeline Delay Register - 0x03. A value of a0 = 160 and the unit is 9.416ns (RF period / 2) so the delay is 1,506ns.
Adjusting the Hit Pipleline Delay¶
- We want to adjust the pipeline to take out about 200ns of delay. Thus we want to reduce the register value by 21 going from 0xa0=160 to 139=0x8B
- The command is "HC 0 WR 3 8B"
HC 0 WR 3 8B hc 0 rdi 0 7 27 ac 8b ffff ffff ffff ffff 380 380 380 380 380 380 380 380 7 27 ac 8b ffff ffff ffff ffff 380 380 380 380 380 380 380 380 7 27 ac 8b ffff ffff ffff ffff 380 380 380 380 380 380 380 380 7 27 ac 8b ffff ffff ffff ffff 380 380 380 380 380 380 380 380 7 27 ac 8b ffff ffff ffff ffff 380 380 380 380 380 380 380 380 7 27 ac 8b ffff ffff ffff ffff 380 380 380 380 380 380 380 380 7 27 ac 8b ffff ffff ffff ffff 380 380 380 380 380 380 380 380 7 27 ac 8b ffff ffff ffff ffff 380 380 380 380 380 380 380 380 7 27 ac 8b ffff ffff ffff ffff 380 380 380 380 380 380 380 380 7 27 ac 8b ffff ffff ffff ffff 380 380 380 380 380 380 380 380 7 27 ac 8b ffff ffff ffff ffff 380 380 380 380 380 380 380 380 7 27 ac 8b ffff ffff ffff ffff 380 380 380 380 380 380 380 380 7 27 ac 8b ffff ffff ffff ffff 380 380 380 380 380 380 380 380 7 27 ac 8b ffff ffff ffff ffff 380 380 380 380 380 380 380 380 7 27 ac 8b ffff ffff ffff ffff 380 380 380 380 380 380 380 380 7 27 ac 8b ffff ffff ffff ffff 380 380 380 380 380 380 380 380
- Then, one needs to store the new setting in flash : "HC 0 DSAV 1"
HC 0 DSAV 1 Setup saved to ATMEL Page 1 Setup saved to ATMEL Page 1 Setup saved to ATMEL Page 1 Setup saved to ATMEL Page 1 Setup saved to ATMEL Page 1 Setup saved to ATMEL Page 1 Setup saved to ATMEL Page 1 Setup saved to ATMEL Page 1 Setup saved to ATMEL Page 1 Setup saved to ATMEL Page 1 Setup saved to ATMEL Page 1 Setup saved to ATMEL Page 1 Setup saved to ATMEL Page 1 Setup saved to ATMEL Page 1 Setup saved to ATMEL Page 1 Setup saved to ATMEL Page 1