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Communicating with the wire chambers » History » Version 14

Michael Kordosky, 08/12/2014 03:50 PM

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h1. Communicating with the wire chambers
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h2. Running the Wire Chamber Mini-DAQ
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setup ftbf
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cd ~ftbf_user/experiments/mc7
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Look in instructions.txt
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When you have a few seconds before a spill (in case you want to type a comment before you start the run)
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./daq-mc7.py
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    Example comment:  Good beam 32 GeV, 100 A. 2.5E+05 at MC7SC1
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This daq fills one data file, appending each spill, until the user stops it.
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h2. Looking at the data, Beam Study
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ssh ftbflx01
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setup cern
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cd ~ftbf_user/experiments/mc7/TkRec
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paw
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exec runtk
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h2. How to do a hard reboot of the WC
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If the wire chamber controller at ftbfwc02 starts refusing connections it may need a reboot:
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* from a browser go to http://ftbf-pdu00.fnal.gov
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* User: admin   Password: <on the board in the CR>
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* Navigate to this screen:
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!ftbfpdu00_control_screen.png!
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* click on "Outlet 6" and then choose "Immediate Reboot" from the menu at the top
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* The state will change to "Off" but will be pending. Wait a little while and refresh the screen or log back in. The WC should be back on.
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h2. The telnet interface
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This is experts only!
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* telnet ftbfwc02.fnal.gov 5000
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** also 5001 - 5003 are available
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* "help" prints the top level help menu. h1,h2,h3 also print help menus
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* "p0" gives a synopsis of the last spill, like so:
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<pre>
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p0
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Controllers Spill Data Header  (5653mS SpillGate)
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 TotalWrdCnt  = 00009F89  (40841 D)
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 SpillCounter = 00000001  (1 D)
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 RTC Year/Mon = E08       (14/08)
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 RTC Day/Hr   = C0F       (12/15)
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 RTC Min/Sec  = F14       (15/20)
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 Trigger Cnt  = 00000110
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 Status Bits  = 0
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 Link Status  = 0
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           TDC Spill Hdrs (1 <= 16)
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 Input   Words       TDCnum   TrgCnt      Status
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   1     00000A9E    0001     00000110    0008
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   2     00000A05    0002     00000110    0008
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   3     00000A2E    0003     00000110    0008
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   4     00000A22    0004     00000110    0008
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   5     000009D2    0005     00000110    0008
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   6     00000A89    0006     00000110    0008
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   7     000009E0    0007     00000110    0008
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   8     00000A32    0008     00000110    0008
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   9     000009D3    0009     00000110    0008
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  10     000009C8    000A     00000110    0008
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  11     000009D3    000B     00000110    0008
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  12     000009B0    000C     00000110    0008
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  13     000009C2    000D     00000110    0008
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  14     000009CE    000E     00000110    0008
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  15     000009B9    000F     00000110    0008
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  16     000009B8    0010     00000110    0008
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</pre>
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* "hc n string" with n=1-16 writes string to TDC n. If n=0 then all TDCs are written to.
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* "hc 0 rdi 0"  writes the command "rdi 0" to all TDCS.  
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** The rdi command is documented in the help menu:  RDI adr c   Read/and Incr FPGA Addr(H), c=WrdCnt(D)
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** The output is:
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<pre>
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hc 0 rdi 0
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   7   27   ac   a0 ffff ffff ffff ffff  380  380  380  380  380  380  380  380 
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   7   27   ac   a0 ffff ffff ffff ffff  380  380  380  380  380  380  380  380 
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   7   27   ac   a0 ffff ffff ffff ffff  380  380  380  380  380  380  380  380 
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   7   27   ac   a0 ffff ffff ffff ffff  380  380  380  380  380  380  380  380 
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   7   27   ac   a0 ffff ffff ffff ffff  380  380  380  380  380  380  380  380 
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   7   27   ac   a0 ffff ffff ffff ffff  380  380  380  380  380  380  380  380 
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   7   27   ac   a0 ffff ffff ffff ffff  380  380  380  380  380  380  380  380 
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   7   27   ac   a0 ffff ffff ffff ffff  380  380  380  380  380  380  380  380 
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   7   27   ac   a0 ffff ffff ffff ffff  380  380  380  380  380  380  380  380 
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   7   27   ac   a0 ffff ffff ffff ffff  380  380  380  380  380  380  380  380 
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   7   27   ac   a0 ffff ffff ffff ffff  380  380  380  380  380  380  380  380 
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   7   27   ac   a0 ffff ffff ffff ffff  380  380  380  380  380  380  380  380 
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   7   27   ac   a0 ffff ffff ffff ffff  380  380  380  380  380  380  380  380 
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   7   27   ac   a0 ffff ffff ffff ffff  380  380  380  380  380  380  380  380 
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   7   27   ac   a0 ffff ffff ffff ffff  380  380  380  380  380  380  380  380 
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   7   27   ac   a0 ffff ffff ffff ffff  380  380  380  380  380  380  380  380 
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</pre>
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** The rows of this readout correspond to the different TDCs.
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** The columns of this readout have a well defined meaning. They correspond to registers in the "FTBF TDC FPGA Register Map" document found at [[TDC Readout Documentation]].  For example:
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*** The first column is the Control and status register - 0x00. 
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*** The second is the gate width register - 0x01. 
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*** The third is the time stamp counter initial value (a.k.a. clock adjust) - 0x03. 
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*** The forth column is the Hit Pipeline Delay Register - 0x03. A value of a0 = 160 and the unit is 9.416ns (RF period / 2) so the delay is 1,506ns.
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h3. Adjusting the Hit Pipleline Delay
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* We want to adjust the pipeline to take out about 200ns of delay. Thus we want to reduce the register value by 21 going from 0xa0=160 to 139=0x8B
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* The command is "HC 0 WR 3 8B"
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<pre>
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HC 0 WR 3 8B
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hc 0 rdi 0
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   7   27   ac   8b ffff ffff ffff ffff  380  380  380  380  380  380  380  380 
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   7   27   ac   8b ffff ffff ffff ffff  380  380  380  380  380  380  380  380 
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   7   27   ac   8b ffff ffff ffff ffff  380  380  380  380  380  380  380  380 
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   7   27   ac   8b ffff ffff ffff ffff  380  380  380  380  380  380  380  380 
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   7   27   ac   8b ffff ffff ffff ffff  380  380  380  380  380  380  380  380 
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   7   27   ac   8b ffff ffff ffff ffff  380  380  380  380  380  380  380  380 
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   7   27   ac   8b ffff ffff ffff ffff  380  380  380  380  380  380  380  380 
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   7   27   ac   8b ffff ffff ffff ffff  380  380  380  380  380  380  380  380 
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   7   27   ac   8b ffff ffff ffff ffff  380  380  380  380  380  380  380  380 
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   7   27   ac   8b ffff ffff ffff ffff  380  380  380  380  380  380  380  380 
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   7   27   ac   8b ffff ffff ffff ffff  380  380  380  380  380  380  380  380 
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   7   27   ac   8b ffff ffff ffff ffff  380  380  380  380  380  380  380  380 
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   7   27   ac   8b ffff ffff ffff ffff  380  380  380  380  380  380  380  380 
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   7   27   ac   8b ffff ffff ffff ffff  380  380  380  380  380  380  380  380 
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   7   27   ac   8b ffff ffff ffff ffff  380  380  380  380  380  380  380  380 
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   7   27   ac   8b ffff ffff ffff ffff  380  380  380  380  380  380  380  380
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</pre>
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* Then, one needs to store the new setting in flash : "HC 0 DSAV 1"
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<pre>
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HC 0 DSAV 1
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Setup saved to ATMEL Page 1
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Setup saved to ATMEL Page 1
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Setup saved to ATMEL Page 1
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Setup saved to ATMEL Page 1
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Setup saved to ATMEL Page 1
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Setup saved to ATMEL Page 1
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Setup saved to ATMEL Page 1
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Setup saved to ATMEL Page 1
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Setup saved to ATMEL Page 1
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Setup saved to ATMEL Page 1
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Setup saved to ATMEL Page 1
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Setup saved to ATMEL Page 1
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Setup saved to ATMEL Page 1
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Setup saved to ATMEL Page 1
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Setup saved to ATMEL Page 1
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Setup saved to ATMEL Page 1
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</pre>