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Communicating with the wire chambers

How to do a hard reboot of the WC controller

If the wire chamber controller at ftbfwc02 starts refusing connections it may need a reboot:

  • if taking a run, stop the DAQ before rebooting the wire chambers
  • from a browser go to http://ftbf-pdu00.fnal.gov
  • User: admin Password: <written on a note on the right side of the central monitor at ROC West, or on the board at MCenter>
  • Navigate to this screen:

  • click on "Outlet 6" and then choose "Reboot Immediate" from the drop-down menu at the top, and click "Next" at the bottom (you will be asked to confirm this decision in the next screen)
  • The state will change to "Off" but will be pending. Wait a little while and refresh the screen or log back in. The WC should be back on.
  • Wait a couple of minutes before starting a new run

The telnet interface

This is experts only! If the problem persists after doing the hard reboot described in the previous section, do a hard reset from the telnet interface.

  • telnet ftbfwc02.fnal.gov 5000
    • also 5001 - 5003 are available
After issuing this command, the prompt will appear blank. Type your command in that blank space.
For a hard reboot, do:
  • FF

If it worked, you will be kicked out. You can re-telnet if you need to perform other operations.
Other useful commands:

  • "help" prints the top level help menu. h1,h2,h3 also print help menus
  • "p0" gives a synopsis of the last spill, like so:
p0
Controllers Spill Data Header  (5653mS SpillGate)
 TotalWrdCnt  = 00009F89  (40841 D)
 SpillCounter = 00000001  (1 D)
 RTC Year/Mon = E08       (14/08)
 RTC Day/Hr   = C0F       (12/15)
 RTC Min/Sec  = F14       (15/20)
 Trigger Cnt  = 00000110
 Status Bits  = 0
 Link Status  = 0
           TDC Spill Hdrs (1 <= 16)
 Input   Words       TDCnum   TrgCnt      Status
   1     00000A9E    0001     00000110    0008
   2     00000A05    0002     00000110    0008
   3     00000A2E    0003     00000110    0008
   4     00000A22    0004     00000110    0008
   5     000009D2    0005     00000110    0008
   6     00000A89    0006     00000110    0008
   7     000009E0    0007     00000110    0008
   8     00000A32    0008     00000110    0008
   9     000009D3    0009     00000110    0008
  10     000009C8    000A     00000110    0008
  11     000009D3    000B     00000110    0008
  12     000009B0    000C     00000110    0008
  13     000009C2    000D     00000110    0008
  14     000009CE    000E     00000110    0008
  15     000009B9    000F     00000110    0008
  16     000009B8    0010     00000110    0008
  • "hc n string" with n=1-16 writes string to TDC n. If n=0 then all TDCs are written to.
  • "hc 0 rdi 0" writes the command "rdi 0" to all TDCS.
    • The rdi command is documented in the help menu: RDI adr c Read/and Incr FPGA Addr(H), c=WrdCnt(D)
    • The output is:
      hc 0 rdi 0
         7   27   ac   a0 ffff ffff ffff ffff  380  380  380  380  380  380  380  380 
         7   27   ac   a0 ffff ffff ffff ffff  380  380  380  380  380  380  380  380 
         7   27   ac   a0 ffff ffff ffff ffff  380  380  380  380  380  380  380  380 
         7   27   ac   a0 ffff ffff ffff ffff  380  380  380  380  380  380  380  380 
         7   27   ac   a0 ffff ffff ffff ffff  380  380  380  380  380  380  380  380 
         7   27   ac   a0 ffff ffff ffff ffff  380  380  380  380  380  380  380  380 
         7   27   ac   a0 ffff ffff ffff ffff  380  380  380  380  380  380  380  380 
         7   27   ac   a0 ffff ffff ffff ffff  380  380  380  380  380  380  380  380 
         7   27   ac   a0 ffff ffff ffff ffff  380  380  380  380  380  380  380  380 
         7   27   ac   a0 ffff ffff ffff ffff  380  380  380  380  380  380  380  380 
         7   27   ac   a0 ffff ffff ffff ffff  380  380  380  380  380  380  380  380 
         7   27   ac   a0 ffff ffff ffff ffff  380  380  380  380  380  380  380  380 
         7   27   ac   a0 ffff ffff ffff ffff  380  380  380  380  380  380  380  380 
         7   27   ac   a0 ffff ffff ffff ffff  380  380  380  380  380  380  380  380 
         7   27   ac   a0 ffff ffff ffff ffff  380  380  380  380  380  380  380  380 
         7   27   ac   a0 ffff ffff ffff ffff  380  380  380  380  380  380  380  380 
      
    • The rows of this readout correspond to the different TDCs.
    • The columns of this readout have a well defined meaning. They correspond to registers in the "FTBF TDC FPGA Register Map" document found at TDC Readout Documentation. For example:
      • The first column is the Control and status register - 0x00.
      • The second is the gate width register - 0x01.
      • The third is the time stamp counter initial value (a.k.a. clock adjust) - 0x03.
      • The forth column is the Hit Pipeline Delay Register - 0x03. A value of a0 = 160 and the unit is 9.416ns (RF period / 2) so the delay is 1,506ns.

Adjusting the Hit Pipleline Delay

  • We want to adjust the pipeline to take out about 200ns of delay. Thus we want to reduce the register value by 21 going from 0xa0=160 to 139=0x8B
  • The command is "HC 0 WR 3 8B"
    HC 0 WR 3 8B
    
    hc 0 rdi 0
       7   27   ac   8b ffff ffff ffff ffff  380  380  380  380  380  380  380  380 
       7   27   ac   8b ffff ffff ffff ffff  380  380  380  380  380  380  380  380 
       7   27   ac   8b ffff ffff ffff ffff  380  380  380  380  380  380  380  380 
       7   27   ac   8b ffff ffff ffff ffff  380  380  380  380  380  380  380  380 
       7   27   ac   8b ffff ffff ffff ffff  380  380  380  380  380  380  380  380 
       7   27   ac   8b ffff ffff ffff ffff  380  380  380  380  380  380  380  380 
       7   27   ac   8b ffff ffff ffff ffff  380  380  380  380  380  380  380  380 
       7   27   ac   8b ffff ffff ffff ffff  380  380  380  380  380  380  380  380 
       7   27   ac   8b ffff ffff ffff ffff  380  380  380  380  380  380  380  380 
       7   27   ac   8b ffff ffff ffff ffff  380  380  380  380  380  380  380  380 
       7   27   ac   8b ffff ffff ffff ffff  380  380  380  380  380  380  380  380 
       7   27   ac   8b ffff ffff ffff ffff  380  380  380  380  380  380  380  380 
       7   27   ac   8b ffff ffff ffff ffff  380  380  380  380  380  380  380  380 
       7   27   ac   8b ffff ffff ffff ffff  380  380  380  380  380  380  380  380 
       7   27   ac   8b ffff ffff ffff ffff  380  380  380  380  380  380  380  380 
       7   27   ac   8b ffff ffff ffff ffff  380  380  380  380  380  380  380  380
    
  • Then, one needs to store the new setting in flash : "HC 0 DSAV 1"
    HC 0 DSAV 1
    Setup saved to ATMEL Page 1
    Setup saved to ATMEL Page 1
    Setup saved to ATMEL Page 1
    Setup saved to ATMEL Page 1
    Setup saved to ATMEL Page 1
    Setup saved to ATMEL Page 1
    Setup saved to ATMEL Page 1
    Setup saved to ATMEL Page 1
    Setup saved to ATMEL Page 1
    Setup saved to ATMEL Page 1
    Setup saved to ATMEL Page 1
    Setup saved to ATMEL Page 1
    Setup saved to ATMEL Page 1
    Setup saved to ATMEL Page 1
    Setup saved to ATMEL Page 1
    Setup saved to ATMEL Page 1
    

Looking at the data, Beam Study OBSOLETE

ssh ftbflx01
setup cern
cd ~ftbf_user/experiments/mc7/TkRec
paw
exec runtk