Choose TDC start time register value such that spurious early hits are removed
Consider how this affects the syncro with other sensors
Note that t0 is the same regardless of start time offset
Timeout mechanism for commands in StrawsDAQ
Try to reproduce 3 TDC problem at UCL
Try then to fix it, particularly by clearing spy buffer between spills (also integrations)
Determine complete system synchro scheme with MWPC/scintillator people
Add TDC power on/off functionality to StrawsDAQ
Get TDC power on/off scheme from Dan
Add hardware trigger functionality to StrawsDAQ
Do we want to do something withthe clock 200 count?
Install Midas at UCL
TDC fine time bit linearity now much improved in new BU TDC firmware
Dan will install this on the TDCs at Fermilab for the test beam
We should also install it here, but we'll need a programming cable. BU can supply us with one.
Dan will increment the firmware version number in the TDC packet header
XML file changes in /unix/muons... DAQ repo need commiting and pushing
Is there a software_ready isssue with sending CONFIGURE commands to TDC (see comments in "configuring" in StrawsDAQ)
Should clk200 and trig_time values be recorded by spftware somewhere?
Do we want to clear sw_ready whilst we read the spy buffer? Think carefully about how this would help with stopping the W ptr overtaking the R ptr
Hardware trig period is gap between trailing edge of one trigger to rising edge of next, so is not actually theperiod between gen_spill commands. The trig length is 40Hz (same as the period unit), so real period is one 1/40s longer. Handle this in register setting?
Need to throw error if gen_spill period is less than accumulation time (also need to consider delay between gen spin and accumulation start, and also readout time)