Prototype ARICH description

ARICH hardware and electronics

Overall ARICH + Electronics wiring diagram shown below. Instructions for power-on is at ARICH_Power-on_and_Power-off_instructions

ARICH has 9 MA-PMTs; MA-PMTs are numbered from 0 to 8, starting in upper left corner, when looking downstream

Each MA-PMT has 4 Padiwa cards plugged into them. Padiwa cards are built by GSI and have discriminators for each MA-PMT channel. We need to configure the discriminator thresholds. Once thresholds are configured, Padiwas will output fast LVDS pulse for each hit. Each Padiwa is powered with 5V; typical current draw per padiwa is ~0.3A, though problems seem to drive current draw above 0.5A sometimes.

LVDS pulses are digitized with FPGA TDC on TRB3 boards (also built at GSI).

The current ARICH/TRB channel mapping is shown in attached file .

TRB Digitizers

We use TRB3 FPGA-based TDC digitizers for the ARICH. For more information on the TRBs, you can see

The emphaticdaq01 is connected to the TRBs on a private network.

The IPs and hostnames of the four TRBs are: trb000 trb001 trb002 trb003

TRBs get their IPs from DHCP server which runs on emphaticdaq01.

There is a useful TRB webpage, which shows various information about the TRBs. But the webserver often dies. To restart it do:

cd /home1/arich/trbsoft/daqtools/web
ps aux | grep httpi
<kill all the zombie processes you see>
./cts_gui --noopenxterm --port=1234 --endpoint=0xc001

Once the webserver is running, you can get various useful information from


In particular, you can check the trigger configuration here


TRB3 configuration

We have four TRBs (numbered 0-3).

The TRBs are organized in a master/slave relationship. trb000 is the master. All configuration goes through trb000 and trb000 distributes the trigger signals to the other TRBs. However, the data packets get sent directly from each TRB to emphaticdaq01.

Each TRB has four peripheral FPGAs and one central FGPA.

On trb000 we have the following configuration for peripherals:

  • FPGA1/FPGA2: 32 channel board TDC digitization, taking two standard flat 34wire ribbon cables.
  • FPGA3: 8 LEMO board TDC digitization, taking either TTL or LVDS signals.
  • FPGA4: SFPAddOn to communicate with other TRBs

trb001, trb002, trb003 have all their peripheral FPGAs configured with AddOn boards for Padiwas.

TRB initialization

Whenever the TRBs are power cycled, they need to be initialized before running. Do this:

cd /home1/arich/online/trb3_configuration/triumf_arich/

The output should include a line about 'number of trb endpoints in the system: 20'

This script is also run at the start of each run.

After running the startup script, you should run the following command to check all 20 FPGAs are responding and that they have the correct identifiers.

[arich@emphaticdaq01 triumf_arich]$ trbcmd i 0xffff
0xc001  0x97000009440aec28  0x05
0x0100  0x23000009440adf28  0x00
0x0101  0xfd000009440ac828  0x01
0x0102  0x12000009440aeb28  0x02
0x0103  0xea000009440ae028  0x03
0xa001  0xcd000009430cbe28  0x05
0x0201  0x2600000942a25a28  0x01
0x0200  0x1100000942a25b28  0x00
0x0202  0xc3000009430cc728  0x02
0x0203  0x8c00000942828328  0x03
0xa002  0x2600000812430728  0x05
0x0302  0xdb00000812419d28  0x02
0x0300  0x1500000812385728  0x00
0x0301  0x1100000812430628  0x01
0x0303  0x5a0000081361ef28  0x03
0xa003  0xc500000a62bf3528  0x05
0x0403  0x2e00000a62bf3028  0x03
0x0400  0xe300000a62bf2928  0x00
0x0401  0xa900000a62bf2428  0x01
0x0402  0x5300000a62bf3c28  0x02

Setting Padiwa thresholds


Safety stuff:

ARICH test stand covered by ORC-1714.