Penn Trigger Board

important remarks

  • A new firmware version is planned to be deployed on Feb 19 2016. This will bring a couple of improvements:
    • Trigger prescales will now be fixed.
    • First microslice in a run will no longer be discarded maintaining synchronization with all other components
    • New internal trigger logic mode is being introduced (NON-UNIQUE).
    • Improved external trigger logic.

(The remarks listed below have now been fixed. The list is kept for reference purposes only.)

There is currently an error in the PTB board reader in parsing a message returned by the PTB when either a configuration or a command (start/stop run) is sent. This error can be ignored as it does not cause a DAQ failure.A fix will be added soon. For the moment these errors are meaningless.
There is a warning with the message: Run start time not yet set. Estimating from the time of the first payload. This warning can be ignored. It will be downgraded to a debug message in the future.
Occasionally there is a warning with the message: _ Incomplete ReceiveMicroslicePayload received for microslice N._. This is a known issue in the board reader but the data is still collected. The warning can be ignored. A fix in the board reader is getting prepared.

General information

There are two PTB's: ptb01 and ptb02. However, only one board is used at a single moment (the other is a spare). This means that there is only one fhicl file and there is no reason to have a second, since the boards are completely identical (including IP address).
The PTB is configured through the file penn01_hw_cfg.fcl. This file contains the default settings for all configurable parameters for all the features of the board. However, this file should never be modified, and any tuning of the parameters should be done by overriding the parameter of interest in file user_run_options.fcl. In the "Tips and Tricks" section below, some specific applications are explained.


Below is a list of definition that might be helpful for the non-muon detector expert user.

  • TSU
    • Muon panels placed on the sides of the cryostat. They are positioned in overlapping pairs due to the high noise rate. Each pair is one channel and a coincidence of both counters is required to consider the channel as being asserted. Placed to look for horizontal muons and have a small event rate.
  • BSU
    • Muon panels placed on the top of the cryostat. They are placed to look for vertical muons and have a high event rate. Each channel is a single panel.
  • MicroSlice
    • Data collected in a configurable time interval. Each event/Millislice corresponds to a given number of MicroSlices, which are not necessarily an integer fraction. This means that one MicroSlice can be split into 2 smaller parts, each going into a different MilliSlice.
  • Millislice
    • Unit of data collected in a larger configurable interval. This has to be maintained in sync with the other readout systems. At the moment it corresponds to a 5 ms span of data.
  • Muon Trigger
    • Event matching a configurable pattern of counters with signal. In the PTB the triggers are configurable through the fhicl file and are constructed in the way explained below.
  • Short and Long NOvA timestamps
    • To reduce the amount of transferred data, only one full timestamp is generated per MicroSlice, which marks the end of the MicroSlice. This is known as the long timestamp or full NOvA timestamp. All other words (Counter, Trigger) use a short version that corresponds to the lower 27 bits of the full timestamp. Since there is 1 full timestamp per MicroSlice and the MicroSlices can never be larger than the largest number represented by 27 bits, it is possible to get the full timestamp for all words, given the microslice reference timestamp. There is code in lbne-raw-dataPennMilliSlice that does this within the Payload_Timestamp structure.

Muon Triggers

Defining muon triggers

The muon triggers are defined in the following way: Two groups of counters are constructed by setting separate bit masks. A logical operation is applied to all the enabled channels of each group producing 2 independent group logic results. Then a third logical operation is applied between the group logic results producing the result of the trigger logic. Finally, if the trigger result is asserted an additional test is made to a prescale parameter to see if the trigger should effectively be generated, or if it should be prescaled.

The selection of the channels that go into individual group of triggers is defined by a channel mask. The logic operations that can be applied within a group are:

Fhicl entry Short name Description
0x01 OR Apply an OR over all the channels enabled in the mask. Result is true if at least one of the masked channels is asserted.
0x10 NON-UNIQUE Result is true if at least two of the masked channels are asserted.
0x11 UNIQUE Result is true if a single masked channel is asserted.

The logic operations that can be applied between groups are:

Fhicl entry Short name Description
0x00 AND Apply an AND over the result of the group operations. Result is true if both groups returned true.
0x01 OR Apply an OR over the result of the group operations. Result is true if at least one of the groups is asserted.
0x10 XOR Apply an XOR to the results of the group operations. Result is true if only one of the group results is true.

Predefined Trigger types

The PTB has logic allocated for 4 different triggers. The specific definition of each trigger is done in the fhicl configuration file. Therefore, the triggers can be changed without need to modify the firmware.
Below is a list of the triggers currently configured:

  • Trigger 0 (aka trigger A)
    • Only one BSU counter in the section RM 1-16 and only one BSU counter in the section CL 1-13
      • Due to the large trigger rate, this trigger should be prescaled so that the DAQ can cope with the data volume from the TPC readout.
  • Trigger 1 (aka trigger B)
    • Any TSU counter in the section NU 1-6 and any TSU counter in the section SL 1-6.
  • Trigger 2 (aka trigger C)
    • Any TSU counter in the section SU 1-6 and any TSU counter in the section NL 1-6.
  • Trigger 3 (aka trigger D)
    • Any TSU counter in the section EL 1-10 and any TSU counter in the section WU 1-10.

fhicl file description

The fhicl file is broken into several sections, each grouping related parameters. In some cases the sections are split into subsections. All the parameters are explained in detail in the file itself, but they are also explained below.


Contains the parameters pertinent for the data transmission between the PTB and the board reader. Should only be modified by a PTB expert.
The parameters are:

  • daq_host
    • The host where the board reader is running.
  • daq_port
    • The port where the board reader is listening.
  • daq_rollover
    • Number of words after which a ethernet packet would be sent to the board reader regardless of having received a timestamp word, generating a fragmented microslice. Not being used at the moment as fragmented micro slices have been disabled.
  • daq_microslice_size
    • Time based rollover. Sets the time interval between full timestamps (and therefore the size of the micro slices).The value is counted in NOvA clock ticks. Can take any value that fits a 27 bit word, but must be smaller than the size of the millislice.


Contains masks indicating which channels are on from the two possible inputs (TSU's and BSU's). In the PTB there are a total of 50 BSU channels and 48 TSU channels. Not all channels are currently in use.

  • BSU
    • 50 bit hex word describing which channels should be read out.
  • TSU
    • 48 bit hex word indicating which TSU channels are to be read by the board.


Contains a single parameter that affects the output. More parameters might be added at a later point.

  • pulse_width
    • Width of all output pulses in counts of NOvA clock (32.250 ns). It takes any integer number between 1 and 63 (32.250-2031.75) ns. This values affects all output pulses (trigger and calibration).


Contains all the parameters pertinent for the muon triggers. There are 4 triggers built in a generic form in the firmware. The specific configuration of the triggers is performed through the parameters below.
Each trigger is configured in a trigger_N subsection.

  • trig_window
    • Integer number of clock ticks that the input muon counter signal is stretched. This is effectively the trigger gate. It takes a value in the range 0-15 which corresponds to a gate of 0-483.75 ns. This value is common to all triggers.
  • trig_lockdown
    • Integer number of clock ticks that the channel is locked down (ignored/masked out) after being part of a trigger gate. Accepts values in the range 0-63 which corresponds to a time range of 0-2031.75 ns. This value is common to all triggers.
  • num_triggers
    • Number of trigger configurations available. This value should only be modified by a PTB expert.

Each trigger is described in an individual subsection. The parameters of the subsection are described below:

  • id
    • Internal reference name. It is used only for debugging purposes.
  • id_mask
    • The mask that is used in the PTB firmware. Currently this mask is hardcoded in the firmware so this parameter is not used.
  • logic
    • The logic that is to be applied to the logical result of each group. Possible values are 0 (AND), 1 (OR), 2 (XOR)
    • Number of triggers that should be ignored/prescaled after a successful trigger of the same type. Accepts an integer in the range 0-255.

Two subsections (group1, group2) are defined, that define the logic to produce the primary group logic. for the trigger. Each group is defined by a bit mask and a logic that is to be applied over all channels of the group. The parameters are:

  • logic
    • Logic to be applied over all enabled channels of the group. Each value represents a type of logic. Valid values are 1 (OR), 3 (UNIQUE)
  • BSU
    • Hex bit mask indicating which BSU channels are part of the group.
  • TSU
    • Hex bit mask indicating which TSU channels are part of the group.


This section configures the external trigger inputs. It's parameters are:

  • mask
    • Hex mask of which inputs trigger channels are valid (or ignored). The MSB corresponds to the channels I1-I8 which are OR-ed.
  • echo_triggers
    • Indicates whether a trigger input should be echoed in the trigger out channels.


Configures the 4 calibration channels. There are 4 subsections, one per channel. Each section is named like the label that is in the front panel of the PTB (C1-4). The parameters are:

  • id
    • An ID used for parsing the configuration. Should not be changed
  • id_mask
    • ID that is passed from the PL. Should not be changed
  • enabled
    • Enables/disables the calibration channel (true = enable, false = disable)
  • period
    • Number of clock ticks between the pulses. Accepts an integer in the range 1-2147483647 which corresponds to something between 32.25 ns and approx. 1 min.

Tips and tricks

In this section some specific instructions are given to do specific tasks. These tasks should be performed in user_run_options.fcl.

Enable/disable channels

To change which channels are read one has to modify the channel masks appropriately. Therefore a new mask should be added to the fhicl file. Below are some specific examples.

  • Disable channels 0 to 16 in the BSU's

The following line should be added to the fhicl file (note the E00 at the end of the mask, identifying the channels masked out):

daq.fragment_receiver.channel_mask.BSU : 0x3FFFFFFFFFE00
  • Disable all BSUs

The following line should be added:

daq.fragment_receiver.channel_mask.BSU : 0x0
  • Disable all channels except BSU ch 4-7 and TSU ch 16-32

The following lines should be added:

daq.fragment_receiver.channel_mask.BSU : 0xF0
daq.fragment_receiver.channel_mask.TSU : 0xFFFF0000

How to change trigger prescales

This is done by modifying the prescale parameter on the trigger of interest. For example, if one wants to prescale trigger A (BSU's) by 3 (meaning that only 1 in every 4 triggers is recorded and sent out to the other systems) one would add the following like to run_user_options.fcl:

daq.fragment_receiver.muon_triggers.trigger_0.prescale : 3

How to disable a trigger

Increasing the prescale of the trigger to the maximum value is a way to "virtually" disable a trigger. The prescale parameter at the moment can go up to 255. However, if the configured trigger has a high rate, it could still cause troubles. Therefore, the most effective way of disabling a trigger is by setting its channel mask to 0x0. For example, the snippet below disables the trigger_2 block (the original code is hidden).

Fhicl block for disabled trigger:

      trigger_1 : {
        id      : "B"     
        id_mask : "0100" 
        logic   : 0x0 
        prescale: 0 
        group1 : {
          logic : 1 
          BSU   : 0x0 
          TSU   : 0x0
        group2 : {
          logic : 1
          BSU   : 0x0 
          TSU   : 0x0