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Feature #23118

No identification of bad bias or mux on display

Added by Glenn Horton-Smith 3 months ago.

Status:
New
Priority:
Normal
Assignee:
-
Start date:
08/14/2019
Due date:
% Done:

0%

Estimated time:
Duration:

Description

The table of voltages shows values but not pass/fail status of tests.
Some information is given when attempt is made to save, but it is often incomplete. (Which FPGA?)



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