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Task #20360

drvgen specification for NML timing module

Added by John Diamond over 1 year ago. Updated over 1 year ago.

Status:
Work in progress
Priority:
Normal
Assignee:
Start date:
07/18/2018
Due date:
% Done:

20%

Estimated time:
2.00 h
Spent time:
Duration:

Description

Should be almost identical to the Booster timing module spec.

History

#1 Updated by John Diamond over 1 year ago

  • Status changed from New to Work in progress
  • Assignee set to John Diamond
  • % Done changed from 0 to 20

Not exactly identical to Booster timing module, not at all. More like the NML trigger board.

Had to divert attention to build support for the TSI-148 VME bridge into the Linux kernel to work with our test board. Found that some changes had to be made to the VME master window configuration in order to work with this chip. Verified that values are returned in network-byte order (just like with the Universe bridge).



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