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Task #20038

ACNET interface for adjusting TSG and ADC channel delays

Added by John Diamond over 1 year ago. Updated over 1 year ago.

Status:
Assigned
Priority:
Normal
Start date:
05/29/2018
Due date:
% Done:

0%

Estimated time:
20.00 h
Duration:

Description

Implement an ACNET interface for adjusting TSG ("house" and "board" level) and ADC channel ("bpm" level) delays.

The trigger delay can be implemented via two hardware-level delays:
  1. A delay of the trigger signal itself via programming the Timing Signal Generator device (TSG)
  2. A channel-level delay on the DAQ module that begins it's count-down after the trigger
A BPM expert will want to specify three different levels of delays:
  1. House delay - the time of flight for the beam from the trigger event to the crate's first BPM. The house delay is typically implemented as an offset for each board delay.
  2. Board delay - Each crate can have multiple DAQ modules and the trigger generated for each DAQ module can be programmed relative to the triggered event via the TSG. Typically the hosue delay is implemented as an offset for each board delay.
  3. BPM/Channel/Cable delay - Each DAQ module channel can delay it's acquisition from the moment it is triggered by a few ADC clock ticks. This is typically used to compensate for the delay incurred by the length of the cables from the BPM pickup to the DAQ module inputs.

Thus, the delay from the trigger event to the moment the signal is digitized by the ADC is - house_delay + board_delay + channel_delay.

Delays should be specified in nanoseconds and scaled by the driver. TSG delays are programmed in RF buckets. DAQ module delays are programmed in ADC clock ticks.

History

#1 Updated by John Diamond over 1 year ago

Right now the only way to set the TSG board delay is via bpmd.conf. See the timeSys.trigger_delays option. DAQSystemInitialization::initialize(..) is the method that loads the board delays from bpmd.conf.



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