ACNET interface for adjusting TSG and ADC channel delays
Implement an ACNET interface for adjusting TSG ("house" and "board" level) and ADC channel ("bpm" level) delays.The trigger delay can be implemented via two hardware-level delays:
- A delay of the trigger signal itself via programming the Timing Signal Generator device (TSG)
- A channel-level delay on the DAQ module that begins it's count-down after the trigger
- House delay - the time of flight for the beam from the trigger event to the crate's first BPM. The house delay is typically implemented as an offset for each board delay.
- Board delay - Each crate can have multiple DAQ modules and the trigger generated for each DAQ module can be programmed relative to the triggered event via the TSG. Typically the hosue delay is implemented as an offset for each board delay.
- BPM/Channel/Cable delay - Each DAQ module channel can delay it's acquisition from the moment it is triggered by a few ADC clock ticks. This is typically used to compensate for the delay incurred by the length of the cables from the BPM pickup to the DAQ module inputs.
Thus, the delay from the trigger event to the moment the signal is digitized by the ADC is - house_delay + board_delay + channel_delay.
Delays should be specified in nanoseconds and scaled by the driver. TSG delays are programmed in RF buckets. DAQ module delays are programmed in ADC clock ticks.