Task #13919
Fix scaling for ring pick MPS thresholds
Description
The PXIE ring pickup MPS thresholds never made sense because they are set in ADC integrated counts. Ning has provided a method for scaling to amps -
Intensity Threshold ( P:MPRLT , P:MPRUT ): I_THR: Register Value for thresholds. Threshold_Setting: D80 Setting (common unit, E10?) for thresholds. GW: Raw Gate Width Reading Revised: I_THR = log_base_C3( ( Threshold_Setting / ( GW * C5 ) - C4 ) / C1 ) * GW / C2 C1 = 0.3660774 C2 = 0.0003773625 C3 = 1.7 C4 = -0.268996 C5 = 4.9932073 C6 = 0 ---- Note: the outside parts of this formula can be done on D80, Otherwise, leave D80 scaling to 1.
History
#1 Updated by John Diamond over 4 years ago
The above formula scales to E10 not Amps.
#2 Updated by John Diamond over 4 years ago
Gate Width should be the gate width as read from the digitizer in raw ADC clock ticks.
#3 Updated by John Diamond over 4 years ago
I came up with the inverse function as -
Threshold_Setting = (C5 * GW) * (C4 + C1 * C3^( (C2 * I_THR) / GW ))
#4 Updated by John Diamond over 4 years ago
- % Done changed from 0 to 80
Implemented support for scaling the MPS upper/lower thresholds inside the front end.
Created a CLI command for specifying scaling parameters:
Created a CLI command for specifying scaling parameters:
vmeintMPSThresholdScaleFilterSet deviceId, scaleMethodStr, c1Str, c2Str, c3Ctr, c4Str, c5Str, c6Str
- deviceId is the intensity device ID
- scaleMethodStr specifies what kind of scaling should be done. The default method is "linear". For the PXIE ring pickups this parameter should be "pxie_ring_pickup".
- c1Str .. c6Str are the scaling coefficients (these are floating-point parameters, they must be passed as strings e.g. "2.0")
- linear: C1 * x / C2 + C3
- pxie_ring_pickup: log_base_C3( ( x / ( GW * C5 ) - C4 ) / C1 ) * GW / C2
#5 Updated by John Diamond over 4 years ago
Add a line of output to vmeintShow to display the MPS threshold scaling information:
Intensity Devices - Toroid Device ID: 0 ADC ID: 0, channel: 0 Readouts: BBB disabled, raw disabled DAQ Source: 0 MPS: Enabled NOT TRIPPED Lower: NaN, Upper: NaN, Edge Threshold: 4096 Threshold Scaling: log_base_C3( (x / (gate_width * C5) - C4) / C1 ) * gate_width / C2, where C1 = 0.366 C2 = 0.000377 C3 = 1.7 C4 = -0.26 C5 = 4.99 (pxie_ring_pickup) Pulse Direction: 0 (-) Pulse Width: 0 ns Time Check: Enabled, margin: 128 clock ticks